VLDB+ manual

Note

This is a working document and is therefore neither final nor complete. It is made available to potential VLDB+ users to provide information and to allow them to provide feedback to the VLDB+ team.

Quick links:

• lpGBT project on espace
• VLDB+ webpage
• VLDB+ project on espace
• lpGBT manual
• Discourse lpGBT support
• lpgbt-support@cern.ch

• 1. Introduction
  • 1.1. VLDB+ goal
  • 1.2. VLDB+ Kit content
• 2. Quick start
  • 2.1. VLDB+ modes of operation
  • 2.2. lpGBT modes of operation
  • 2.3. FeastMP DC/DC
  • 2.4. VTRx+ connection
  • 2.5. I2C communication
  • 2.6. Power on the VLDB+
  • 2.7. Configure the lpGBT
  • 2.8. Configure your back-end
  • 2.9. Is it ready?
• 3. Overview
• 4. lpGBT and VTRx+
  • 4.1. lpGBT
  • 4.2. VTRx+
• 5. FEASTMP DC/DC
• 6. VLDB+ switches
  • 6.1. lpGBT Modes
  • 6.2. I2C pull-ups
• 7. VLDB+ powering modes
  • 7.1. Standalone mode
    • 7.1.1. FMC use in Standalone mode
  • 7.2. FMC mode
• 8. lpGBT’s slow control
  • 8.1. RPI and Dongle connector
  • 8.2. ADC
    • 8.2.1. VTRx+ RSSI jumper
  • 8.3. GPIO
  • 8.4. DAC
  • 8.5. External Control
    • 8.5.1. LpGBT-SCA communication guide
• 9. FMC side
  • 9.1. Two HPC
    • 9.1.1. Available signals
    • 9.1.2. Matched lengths
  • 9.2. Protection switches
  • 9.3. EEPROM
• 10. SMA connectors
• 11. TestOut signals
• 12. Fusing
• 13. Appendix
  • 13.1. ECLK signals on FMC
  • 13.2. EDIN signals on FMC
  • 13.3. EDOUT signals on FMC
  • 13.4. PSCLK signals on FMC
  • 13.5. Slow Control signals on FMC
  • 13.6. Miscellaneous signals on FMC
  • 13.7. Protection switches
  • 13.8. lpGBT configuration pins
    • 13.8.1. VLDB+ V1.1 (lpGBT V0)
    • 13.8.2. VLDB+ V2 with lpGBT V0
    • 13.8.3. VLDB+ V2 with lpGBT V1
  • 13.9. lpGBT I2C pull-ups
  • 13.10. High speed signals
  • 13.11. Slow control signals on VLDB+
  • 13.12. VLDB+ switches
  • 13.13. VLDB+ jumpers
  • 13.14. VLDB+ connectors
  • 13.15. VLDB+ push buttons
  • 13.16. VLDB+ testpoints
  • 13.17. VLDB+ electrical characteristics
  • 13.18. Constraints file
• 14. Known issues
  • 14.1. VLDB+ V1.1
    • 14.1.1. Silkscreen
    • 14.1.2. ESD
    • 14.1.3. ECLK0 and PSCLK0 signal integrity
    • 14.1.4. Warning LED1 is lit when the VLDB+ is turned off
    • 14.1.5. Fusing process
    • 14.1.6. Power Good on KCU105/VCU108/VCU118
    • 14.1.7. Carrier Card - VLDB+ standoff holes don’t match
    • 14.1.8. The lpGBT doesn’t reset after a VLDB+ power cycle
  • 14.2. VLDB+ V2
    • 14.2.1. Unsolder and resolder the lpGBT may affect the board functionality
    • 14.2.2. Abruptly disconnecting the RPI-VLDB+ ribbon cable can damage the lpGBT I2C Slave
    • 14.2.3. SW9 had assembly problems in the last VLDB+ batch
• 15. Credits
  • 15.1. VLDB+ Design Team
• 16. Version History