14. Known issues¶

14.1. VLDB+ V1.1¶

All issues listed below are fixed in the VLDB+ V2. Some resistor values were modified in the V1.0 to get the V1.1 working better (there is no existing VLDB+ V1.0).

14.1.1. Silkscreen¶

First issue:

Issue: REFCLKP/N silkscreen is mistaken. REFCLK_P is on the right SMA connector and REFCLK_N in the left one.

Workaround: Connect the SMA cables in the right polarity (inverse way than silkscreen) to provide an external clock to the lpGBT.

Second issue:

Issue: P1V2EN silkscreen close to the J13 connector is misunderstanding as this signal enables/disables both FEASTMPs.

Workaround: None

14.1.2. ESD¶

Issue: In some cases, when touching with a multimeter probe to any of the VLDB+ GND testpoints and having the Raspberry PI connected to the VLDB+, the lpGBT resets. This is due to an ESD discharge on the VLDB+ GND, making the VDD voltage to oscillate. If the Raspberry PI is connected, the RSTB also oscillates making the lpGBT to reset.

Workarounds:

Disconnect the Raspberry PI cable of the J13 connector before probing with the multimter.
Discharge the multimeter on a GND bracelet before probing.

14.1.3. ECLK0 and PSCLK0 signal integrity¶

Issue: The signal integrity of the ECLK0 and PSCLK1 signals is not the expected one (low rises times, visible reflections).

Workaround: None.

14.1.4. Warning LED1 is lit when the VLDB+ is turned off¶

Issue: The LED1 is lit to warn that Vadj > 1.3 V. However, when the VLDB+ is turned off and connected to a turned on FPGA Evaluation Kit with a Vadj below 1.3 V, it’s also lit.

Workaround: None. In any case, please, ensure that Vadj < 1.3 V when connecting an FPGA Evaluation Kit.

14.1.5. Fusing process¶

Issue: The fusing process where you connect a jumper to W16 and you press the PB2 during the required time to supply 2.5 V is not reliable and not recommended to use it at all.

Workaround: We provide a better way to fuse the lpGBT housed on a VLDB+ which is the process described on the Section 12 using the Raspberry PI 4 and the RPI Translator Board V2b. Please, contact lpgbt-support@cern.ch if you want to fuse your lpGBT housed on the VLDB+ to avoid problems.

14.1.6. Power Good on KCU105/VCU108/VCU118¶

Issue: The signal PowerGood Carrier to Mezzanine (PG_C2M) is used on the VLDB+ to enable both FEASTMPs when a Xilinx FPGA Evaluation Kit is connected and turned on. We noticed that using the KCU105, VCU108 and VCU118 Evaluation Kits, the PG_C2M signal is pulled low when VADJ < 1.8 V making the VLDB+ V1.1 uncompatible with these evaluation kits as the FEASTMPs don’t turn on when VADJ = 1.2V (VADJ is automatically set to 1.2V with these Evaluation Kits as the IC3 EEPROM is configured with this VADJ value).

Workaround: We had to cut the PG_C2M track, J2-D1, going through the FMC HPC2 so the FEASTMPs can be enabled through the VIN_VLDB+ and the Zener diode D1 only.

14.1.7. Carrier Card - VLDB+ standoff holes don’t match¶

Issue: Due to a design problem, no standoffs can be put between the FPGA evaluation kit and the VLDB+ when they are connected through both FMC-HPC as the holes on the VLDB+ don’t match the ones of any VLDB+-compatible FPGA evaluation kit.

Workaround: None. However, the VLDB+ can be connected to an FPGA evaluation kit without the need of putting standoffs.

14.1.8. The lpGBT doesn’t reset after a VLDB+ power cycle¶

Issue: The lpGBT doesn’t reset after a VLDB+ power cycle through the SW10. This can be noticed by powering down the VLDB+ when the lpGBT is on Ready state and turn it on again: the lpGBT will go to Ready state automatically again (no register values reset, no state-machine reset).

Workaround: This behaviour is due to the supply voltage the RPI Translator Board can provide through the ribbon cable (VDD1V2=~300 mV when VLDB+ turned off), more specifically through the SDA/SCL and VDD lines when using the BRD-1V2 source selection mode (jumper on the left side of the J3). An easy solution is to use the OUT-1V2 mode (put jumper on the right side of the J3) in the Translator Board. Another solution is to remove the ribbon cable when the VLDB+ is off before turning it on again.

14.2. VLDB+ V2¶

14.2.1. Unsolder and resolder the lpGBT may affect the board functionality¶

Issue: It has been seen the unsoldering and resoldering process of different lpGBTs on the same VLDB+ may destroy the SW10 functionality during the preheating process.

Workaround: Remove the SW10 before heating the PCB.

14.2.2. Abruptly disconnecting the RPI-VLDB+ ribbon cable can damage the lpGBT I2C Slave¶

Issue: Experience has shown the RPI Kit - VLDB+ system must have a common ground to avoid instabilities. When this cannot be ensured (i.e VLDB+ Kit - FPGA power connection and FPGA - RPI Kit not having the same power supply), disconnecting the ribbon cable while the whole system still powered can create ground currents that can affect the I2C pins of the lpGBT. As the SCL pin is the most fragile pin of the lpGBT V0, this one is usually damaged by taking this action.

Workaround: Never disconnect the ribbon cable while the RPI Kit is powered. Turn off the RPI Kit before, then remove the ribbon cable. In any case, when possible, ensure to have a common ground for the RPI Kit - VLDB+ system.

14.2.3. SW9 had assembly problems in the last VLDB+ batch¶

Issue: The assembly of SW9 caused issues on some boards. Sometimes the pins of SW9 were removing part of the pads causing the switch to be loose. The SW9 in the boards of this last batch were glued to the PCB. In addition, a few switches had to be resoldered with wires. Nevertheless the integrity of SW9 and its functionality are fully guaranteed.

Workaround: No problems should appear. In any case use SW9 with care.