2. Quick start

The lpGBT is a highly flexible device; it has many settings to be configured. The VLDB+ offers the possibility to test almost all of them. The operation flow for any type of VLDB+ use has to be the same as the one showed in this chapter.

2.1. VLDB+ modes of operation

The mode of operation of the VLDB+ is the first decision to take. The simplest mode to start working with the VLDB+ is the Mode 1: Standalone where the board is powered through an external power supply. We keep the VLDB+ turned off for the moment. Please refer to the Section 7 for more information.

2.2. lpGBT modes of operation

  1. The lpGBT chip can operate in one of several major modes: transmitter, receiver and transceiver. You can already select the mode of operation through the SW7 of the VLDB+. In our case, we will work in transceiver mode, 10 Gbps and FEC12, thus, you have to set the SW7 to ‘1111’ (Modes), that is to move all the switches to the ON position.
  2. For the communication mode, we propose you to select the I2C communication mode to program the lpGBT, that is to move the first switch of the SW8 to the ON position (SC-I2C = ‘1’).
  3. You can add two I2C pull-up resistors through the first two switches of the SW5. This is needed if you are using an I2C master system where you do not have the necessary pull-up resistors. The RaspberryPi4 translator board and the Dongle has them so you do not need to enable these switches.
  4. You can put your desired lpGBT’s I2C and IC/EC address by moving the SW6 switches. For instance, whether you do not move any switch (‘0000’), the lpGBT address will be 0b1110000.
  5. There are two different ways to provide a clock to the lpGBT, either through the data stream (reference-less locking mode) or from an external clock (external 40 MHz). Depending on your lpGBT mode, you have to select one of these to work. If you are in transceiver mode, the only way to obtain a clock is from the data stream, that is to move the second switch of the SW8 to the ON position, LOCKMODE = ‘1’.
  6. Finally, we will leave the third and fourth switches of the SW8 disabled. These switches are called StateOverride and PowerOnResetDisable. They are normally used for lpGBT testing purposes. In normal conditions, these switches have to be always disabled.

Note

In the VLDB+ V2, depending on the lpGBT version housed on it, you might use the SW8 differently. The VCOBYPASS, SC-I2C and STATEOVRD pins are used in the lpGBT V0 however BOOTCNF[0:1] and EDINECTERM are used in the lpGBT V1.

2.3. FeastMP DC/DC

The VLDB+ cannot run without any DC/DC. The DC/DC connectors are located in the top left side of the VLDB+. The silkscreen describes where to plug each DC/DC. You have to plug the FEASTMP1.2 and the FEASTMP2.5 on their respective connectors.

Warning

Both FEASTMP connectors are identical. Take care, do not plug and power the VLDB+ with any FEASTMP plugged in the wrong connector.

2.4. VTRx+ connection

Connect the VTRx+ module to the J14 connector if it is not already connected. Connect the fibers going out the VTRx+ to your back-end transceiver (usable Evaluation Kits on the Table 7.1). To connect the VTRx+ MT connector to the LC fibers, an MPO Fanout Patchcord and two MPO guide pins are needed. You can request these tools on OETEK. Connect the LC fiber #7 to the FPGA TX and the LC fiber #6 to the FPGA RX.

To connect the VTRx+ MT connector to an MPO connector, you have to put the guide pins inside the MPO connector. Then, take a look at the keys from the MPO and MT connectors, both must be in opposite directions. In Fig. 4.6 a picture showing the correct connection is shown.

Refer to Section 4.2 for more information.

Warning

The J14 connector has not a high durability. Please, avoid to connect and disconnect the VTRx+ repeatedly in order to preserve its durability.

2.5. I2C communication

For the lpGBT’s I2C communication, we strongly recommend the use of the RaspberryPi 4 device together with the RPI translator board V2 (to translate 3.3 V to 1.2 V). Connect the 10 pins cable between the J13 connector of the VLDB+ and the level translator board that is, at the same time, connected to the RaspberryPI 4 IO. The VLDB+ J13 connector is also compatible with an 8 pins cable, that is, the Dongle connector (the one used in the former VLDB). To use a Dongle to communicate to the lpGBT, you have to regulate the potentiometer P1 to ~1.2V and adapt the following scripts.

2.6. Power on the VLDB+

As we have chosen the Mode 1: Standalone, we have to externally power the VLDB+. Connect a power supply to the J3 connector. Use the Phoenix connector (Phoenix 1757019) plugged onto it. Ensure that the GND cable is connected in the left side and the VIN cable in the right side. Set the power supply’s output voltage to 10 V, as it is the most efficient input value for them. Set a maximum current of around 200 mA. Power on your power supply and switch on the SW10 to the bottom of the VLDB+, that is, to the Mode1.

Warning

Do not set any VLDB+ mode without the knowledge of its functionality. Risk of permanent damage. Refer to Section 7.

2.7. Configure the lpGBT

You can now configure your lpGBT through the RaspberryPi 4 and piGBT web application. Please refer to the piGBT manual to control your lpGBT and configure it with the quickstart configuration.

Note

The HSOUT polarity is inverted with respect to the VTRx+ TX. If you want to make your back-end lock to the lpGBT upstream data, you have to invert the HSOUT polarity through the [0x036] ChipConfig. For more information refer to the Section 13.10.

2.8. Configure your back-end

You have to configure your FPGA with a valid firmware to make the lpGBT lock to the coming data stream. We provide a validated FPGA firmware that you can adapt depending of your FPGA. Please refer to the GBT-FPGA Git.

2.9. Is it ready?

If you reached this step, the lpGBT should be on 18.Ready state after programming it. Also, your back-end should be locked to the lpGBT upstream.

Note

Any problem? Contact lpgbt-support@cern.ch or look at Discourse lpGBT support.